1. Field of the Invention
The present invention relates to a multi-layer capacitor and, more particularly, to a multi-layer capacitor which can be advantageously used in high frequency circuits.
2. Description of the Related Art
Conventional multi-layer capacitors include those described in Japanese Unexamined Patent Publication No. H2-256216 in which a multi-layer capacitor 1, as shown in FIGS. 15 through 17 of the present application, is disclosed. FIG. 15 is a plan view of the external appearance of the multi-layer capacitor 1. FIG. 16 is a plan view of a first section of the multi-layer capacitor 1 showing a first electrode 10 located on one surface of one internal dielectric layer 9 of the capacitor 1. FIG. 17 is a plan view of a second section of the multi-layer capacitor 1 showing a second electrode 11 located on one surface of a differential internal dielectric layer 9 of the capacitor 1.
Referring to FIGS. 15-17, the multi-layer capacitor 1 includes a capacitor main body 8 in the form of a rectangular parallelpiped having two principal surfaces 2 and 3 in a face-to-face relationship with each other and four side surfaces 4, 5, 6 and 7 connecting the principal surfaces 2 and 3. The capacitor main body 8 includes a plurality of dielectric layers 9 (FIGS. 16-17) made of, for example, a ceramic dielectric material. Each of the dielectric layers is generally planar in shape and lies generally parallel to the principal surfaces 2 and 3. At least a pair of first and second internal electrodes 10 and 11 are provided on respective surfaces of the dielectric layers 9 in a face-to-face relationship with each other, with a dielectric layer 9 interposed therebetween to form a capacitor unit.
The first internal electrode 10 is formed with four lead electrodes 12, 13, 14 and 15 which extend to two opposing side surfaces 4 and 6, as shown.
Each lead electrode 12, 13, 14 and 15 is coupled to a respective external terminal electrode 16, 17, 18 and 19 provided on the side surfaces 4 and 6 of the capacitor main body 8. Specifically, the lead electrodes 12 and 13 are connected to the external terminal electrodes 16 and 17, respectively, which are located on the side surface 4, and the lead electrodes 14 and 15 are connected to the external terminal electrodes 18 and 19, respectively, which are located on the side surface 6.
Referring to FIG. 17, the second internal electrode 11 is also formed with four lead electrodes 20, 21, 22 and 23 which extend to the side surfaces 4 and 6, respectively. More specifically, the lead electrodes 20 and 21 extend to positions on the side surface 4 which are different from the positions to which the lead electrodes 12 and 13 extend, and the lead electrodes 22 and 23 extend to positions on the side surface 6 of the main body 8 which are different from the positions to which the lead electrodes 14 and 15 extend.
The lead electrodes 20 through 23 are electrically coupled to external terminal electrodes 24, 25, 26 and 27, respectively. External terminal electrodes 24 and 25 are located on the side surface 4 at positions which are different from those of the external terminal electrodes 16 and 17. External terminal electrodes 26 and 27 are located on the side surface 6 at positions which are different from the positions of the external terminal electrodes 18 and 19.
Thus, the plurality of first external terminal electrodes 16 through 19 and the plurality of second external terminal electrodes 24 through 27 are arranged on the two side surfaces 4 and 6 such that they alternate adjacently to each other.
FIG. 18 illustrates current flowing through the multi-layer capacitor 1 as viewed in plan view corresponding to FIG. 17. In FIG. 18, first internal electrode 10 and second internal electrode 11, shown with broken and solid lines, respectively, are shown in an overlapping relationship.
In FIG. 18, the arrows indicate typical current paths and directions. In the state illustrated, current flows from each of the external terminal electrodes 24 through 27 to each of the external terminal electrodes 16 through 19. Because an alternating current is used, the direction of current flow will reverse periodically.
When the currents flow, magnetic flux is induced. The direction of the flux is determined by the direction of the currents to produce self-inductance components. Since the currents flow in various directions at central regions 28 (indicated by circles) of the internal electrodes 10 and 11, the induced magnetic flux generated by the various currents is canceled and substantially no net magnetic flux is produced in those regions.
The current in the vicinity of each of the external terminal electrodes 16 through 19 and 24 through 27 tends to flow toward each of the external terminal electrodes 16 through 19 and away from each of the external terminal electrodes 24 through 27. There are currents that flow to the left and right as viewed in FIG. 18 to spread at an angle of about 180 degrees. As a result, a major part of magnetic flux is canceled and there is no significant generation of net magnetic flux in these areas.
Therefore, in the multi-layer capacitor 1 shown in FIGS. 15 through 17, the generation of self-inductance is suppressed in the areas points described above to reduce equivalent series induction (hereinafter "ESL").
However, currents flow substantially in the same direction in the vicinity of each of the side surfaces 5 and 7 on which no external terminal electrodes are provided, i.e., at each of the left and right edge portions indicated by hatching in FIG. 18. This results in substantially no cancellation of magnetic flux in these areas and significant net self-inductance is created. Therefore, the measures taken to reduce ESL in the multi-layer capacitor 1 shown in FIGS. 15 through 17 are less than desirable.